The output W for the given logic circuit is: | vedclass

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(D) $1$. The inputs $X$ and $Y$ are fed into an $OR$ gate. The output of the $OR$ gate is $(X + Y)$.$2$. This output $(X + Y)$ is then passed through

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Both $(B)$ and $(C)$

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(D) $1$. The inputs $X$ and $Y$ are fed into an $OR$ gate. The output of the $OR$ gate is $(X + Y)$.$2$. This output $(X + Y)$ is then passed through a $NOT$ gate (indicated by the bubble at the input of the $AND$ gate,or if we interpret the circuit as having a $NOR$ gate followed by an $AND$ gate). Looking at the diagram,the $OR$ gate output is inverted before entering the $AND$ gate. Thus,the input to the $AND$ gate from the first part is $\overline{X+Y}$.$3$. The other input to the $AND$ gate is $Z$.$4$. The final output $W$ of the $AND$ gate is the product of its inputs: $W = (\overline{X+Y}) . Z$.$5$. According to De Morgan's Law,$\overline{X+Y} = \overline{X} . \overline{Y}$.$6$. Therefore,$W = (\overline{X} . \overline{Y}) . Z$.$7$. Since both expressions $(B)$ and $(C)$ are equivalent,the correct option is $(D)$.

The output $W$ for the given logic circuit is:

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