Draw the output signals C_1 and C_2 for the g | vedclass

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(D) For the first circuit,the input $A$ and $B$ are passed through $NAND$ gates acting as $NOT$ gates,resulting in $\bar{A}$ and $\bar{B}$. These are

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(D) For the first circuit,the input $A$ and $B$ are passed through $NAND$ gates acting as $NOT$ gates,resulting in $\bar{A}$ and $\bar{B}$. These are then fed into a $NAND$ gate,giving $\overline{\bar{A} \cdot \bar{B}} = A + B$. This is then passed through another $NOT$ gate ($NAND$ as $NOT$),resulting in $C_1 = \overline{A + B} = \bar{A} \cdot \bar{B}$. Thus,$C_1$ is high $(1)$ only when both $A$ and $B$ are low $(0)$. Looking at the input graphs,$A=0$ and $B=0$ only in the interval $t = 4 \ s$ to $5 \ s$. Therefore,$C_1$ is high from $4 \ s$ to $5 \ s$.For the second circuit,the inputs $A$ and $B$ are passed through $NOR$ gates acting as $NOT$ gates,resulting in $\bar{A}$ and $\bar{B}$. These are then fed into a $NOR$ gate,giving $C_2 = \overline{\bar{A} + \bar{B}} = A \cdot B$. Thus,$C_2$ is high $(1)$ only when both $A$ and $B$ are high $(1)$. Looking at the input graphs,$A=1$ and $B=1$ only in the interval $t = 1 \ s$ to $2 \ s$. Therefore,$C_2$ is high from $1 \ s$ to $2 \ s$.Comparing this with the given options,the correct output signals match option $D$.

Draw the output signals $C_1$ and $C_2$ for the given combination of logic gates. (Up to $5 \ s$)

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