Consider the following logic circuit. The out | vedclass

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(A) From the circuit diagram,the output of the $AND$ gate is $Y_1 = A \cdot B$.The inputs to the $OR$ gate are $B$ and $\overline{A}$,so its output is

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$A = 1$ and $B = 1$

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(A) From the circuit diagram,the output of the $AND$ gate is $Y_1 = A \cdot B$.The inputs to the $OR$ gate are $B$ and $\overline{A}$,so its output is $Y_2 = \overline{A} + B$.These two outputs $Y_1$ and $Y_2$ are fed into a $NAND$ gate,so the final output is $Y = \overline{Y_1 \cdot Y_2} = \overline{A \cdot B} \cdot \overline{(\overline{A} + B)}$ is incorrect; the correct expression is $Y = \overline{Y_1 \cdot Y_2} = \overline{(A \cdot B) \cdot (\overline{A} + B)}$.Simplifying the expression: $Y = \overline{A \cdot B \cdot \overline{A} + A \cdot B \cdot B} = \overline{0 + A \cdot B} = \overline{A \cdot B}$.For $Y = 0$,we need $\overline{A \cdot B} = 0$,which implies $A \cdot B = 1$.This occurs only when $A = 1$ and $B = 1$.

Consider the following logic circuit. The output is $Y = 0$ when

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